The present invention relates, in general, to the field of data processors and methods. More particularly, the present invention relates to an output compare system and method for automatically controlling multiple outputs in a microprocessor (MPU) or microcomputer (MCU) in which a single output compare function may directly control multiple output pins by means of mask and data registers.
In former MPU and MCU systems, there have been provided output compare functions to generate a timed output signal from the device. Such output signals could be used to either (1) set the output, (2) clear the output, (3) toggle the output, or (4) indicate no change to the output. In certain prior art MCU devices, such as the MC6801 available from Motorola, Inc., assignee of the present invention, there was only one output compare function provided. In the MC6801U4, likewise available from Motorola, Inc., three output compare functions were provided each of which operated as a separate independent entity. In this latter instance, were an output pin not being used for a compare function, control of that pin could not be picked up by one of the other output compare functions.
With such independent prior art output compare functions, the best pulse width available on a given output compare pin was on the order of approximately 30 MCU cycles. This relatively long pulse width is due to the fact that after an output compare occurred on a given pin, an interrupt routine would be executed to write a new higher value to the compare register. Because of this, it was not possible to achieve a one-MCU-cycle wide pulse positioned with one cycle resolution.
Certain other prior art devices, such as the Intel 8096, utilize a content addressable memory. Such content addressable memories are similar to the above-described output compare registers except that they have a circular FIFO configuration in which a value placed therein is sequentially compared against each one of the compare registers in the device to a timer count. Upon achieving a match with the compare register and timer count, a command word associated with the compare value generates an appropriate output signal. By use of this circular FIFO system, the device can set several of its compare registers to the same value and utilize the appropriate command word to cause an action on separate pins so that several of the device pins can change state during the same cycle. However, in utilizing a system of this sort, more than one compare register must be utilized. Still further, such a system is not efficient in effectuating a one-cycle pulse width nor allowing the utilization of any unused output pins on the timer port as timed output pins controlled by a separate output compare register.